A limited number of technologies are typically used in the microelectronics industry to provide electrical and mechanical interconnection to microelectronic devices such as integrated circuit chips. These technologies typically include tape automated bonding (TAB), wire bonding and controlled collapse chip connection (C4). Of these three connection technologies, C4 technology is capable of handling the highest density of input/output (I/O) pads because it typically uses a two-dimensional and closely spaced array of solder bumps to cover an entire surface of an integrated circuit chip. In particular, C4 technology typically utilizes solder bumps formed on wettable metal pads on a chip and a mirror image footprint of wettable metal pads on an opposing substrate to which the chips are soldered. Because the chips are typically soldered face-down to a substrate, C4 technology is typically referred to as "flip-chip" technology. C4 technology offers additional advantages because the shorter interconnect distances provided by the closely spaced bumps yield faster signal response time, low inductance and reduced simultaneous switching noise. The evenly distributed array of solder bumps can also be utilized to provide uniform power and heat distribution. Chip design flexibility is also improved using flip-chip technology.
Fabrication of lead-tin (PbSn) C4 solder bumps by evaporation using a metal mask was originally pioneered by IBM in the mid 1960s. However, evaporation is typically an inefficient technique since often more than 95% of the evaporated material ends up on the walls of the evaporator and metal mask. To address this problem, many techniques for electroplating solder bumps have been proposed as alternatives to evaporation. In these electroplating techniques, a blanket under-bump metal (UBM) layer is typically deposited on a microelectronic substrate (e.g., wafer) by evaporation or sputtering. This continuous UBM layer is typically provided on the contact pads and between the pads so that plating current can be drawn laterally through the UBM layer to the edge of the wafer where it is typically collected by a plurality of circumferentially spaced contact pins. The use of contact pins to withdraw lateral current from a UBM layer is more fully described in U.S. Pat. No. 5,342,495 to Tung et al. entitled Structure for Holding Integrated Circuit Dies to be Electroplated.
In order to define the sites for solder bump formation over the contact pads, a thick layer of photoresist is deposited on the UBM layer and then photolithographically patterned to expose portions of the UBM layer extending opposite the contact pads. Solder bumps are then formed by electroplating the exposed portions of the UBM layer. The portions of the UBM layer extending between the solder bumps are then etched (using the solder bumps as an etching mask) to break the electrical connection between the solder bumps. As will be understood by those skilled in the art, the patterning and etching steps define the geometry of the resulting UBM contact regions which provide electrical and mechanical connections between the solder bumps and the contact pads.
A recently developed electroplating technique is also described in an article by Datta et al. entitled Electrochemical Fabrication of Mechanically Robust PbSn C4 Interconnections, J. Electrochem. Soc., Vol. 142, No. 11, pp. 3779-3785, November (1995). In particular, the Datta et al. article describes a process in which a continuous seed layer is vacuum deposited over a patterned silicon dioxide or polyimide layer on a face of an integrated circuit chip. A thick dry film photoresist layer is then laminated over the seed layer and patterned to define the desired C4 pattern as openings in the photoresist layer. Solder bumps are then formed on the seed layer by electroplating a PbSn solder alloy into the openings using the patterned photoresist layer as a plating mask. The seed layer is then removed to isolate the C4 solder bumps. As described by Datta et al., the seed layer performs a dual function because it provides an electric current path for electrodeposition and, after being etched, it becomes the ball limiting metallurgy (BLM) for the solder bumps by providing both mechanical and electrical connection to the chip. The seed layer is also described as comprising at least two layers: an adhesion layer and a solderable layer. These layers are each described as having thicknesses in a range between about 0.1-0.5 .mu.m (1000-5000 .ANG.).
Another technique for electroplating solder bumps is described in an unexamined Japanese patent application No. 05-166815 by Matsumura, entitled Plating Bump Formation Method and Wafer Plating Jigs. The Matsumura application describes using a backside contact to draw plating current through a wafer 5. The plating current is drawn in a vertical direction through a plurality of wafer dicing streets or scribe lines 5a which are patterned between adjacent chips. In particular, a barrier metal layer 9 is formed over an entire surface of the wafer 5 using a sputter vapor deposition technique. The barrier metal layer 9 contacts the wafer 5 at the dicing streets 5a and provides a conductive path for the plating current to enter the substrate.
The technique described by Matsumura exposes the wafer surface during back-end processing steps. However, exposure of the surface of a wafer between adjacent chips can be difficult from a process standpoint when performed at the end of processing, and can result in reduced chip yield and wafer contamination. Moreover, in order to provide a low resistance lateral current path, the barrier metal layer 9 may need to be relatively thick, which means that subsequent removal of the barrier metal layer 9 may also be difficult and lead to over-etching of regions adjacent and underlying the barrier metal layer 9 and solder bumps. Parasitic Schottky contacts may also form between the barrier metal layer 9 and the exposed dicing streets and cause a reduction in the rate of electroplating and uniformity of the electroplated solder bumps.
Other techniques for electroplating solder bumps are also described in articles by Rinne et al. entitled Advanced Solder Flip Chip Processes, Proc. Surface Mount International: Advanced Electronics Manufacturing Technologies, San Jose, Calif., Vol. 1, pp. 282-292, September (1996); Adema et al. entitled Flip Chip Technology: A Method for Providing Known Good Die with High Density Interconnections, Proc. 3rd International Conference on Multichip Modules, SPIE Vol. 2256, pp. 41-49 (1994); Yung et al. entitled Electroplated Solder Joints for Flip-Chip Applications, IEEE Trans. on Components, Hybrids and Manufacturing Tech., Vol. 14, No. 3, pp. 549-559, September (1991); and Yung et al. entitled Flip-Chip Process Utilizing Electroplated Solder Joints, Proc. 1990 International Electronics Packaging Conference, Marlborough, Mass., pp. 1065-1079, September (1990). Commonly assigned U.S. Pat. Nos. 5,162,257 and 5,293,006 to Yung also describe methods of electroplating solder bumps for flip-chip applications, the disclosures of which are hereby incorporated herein by reference.
An article by Lin et al. entitled Approaching a Uniform Bump Height of the Electroplated Solder Bumps on a Silicon Wafer, IEEE Trans. on Components, Packaging and Manufacturing Tech.--Part B, Vol 19., pp. 747-751, No. 4, November (1996), also describes an electroplating cell design for achieving uniform solder bump height by manipulating the plating current density through individual solder bumps. In particular, according to Lin et al, the uniformity of the thicknesses of the electroplated solder bumps can best be achieved by manipulating the ratio between the width of the silicon wafer and the width of the electrolytic bath exposed to the wafer during the electroplating step.
However, notwithstanding these conventional electroplating techniques, there still continues to be a need for methods of electroplating solder bumps which do not require the exposure of dicing streets during back-end processing or the fabrication of elaborate electroplating cell designs for manipulating the plating current density through individual solder bumps.